Courses & Projects by Rob Marano

ECE 251 Spring 2026 Weekly Course Notes

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Course Schedule

Week(s)	Dates	Topic
1	1/22	Computer Abstraction & Stored Program Concept
2, 3	1/29, 2/5	Instructions —The Language & Grammar of Computers
4, 5	2/12, 2/19	Hardware Modeling with Software (Verilog HDL)
6, 7	2/26, 3/5	Intro to Assembly Language Programming — MIPS CPU
8	3/12	Arithmetic and Floating Point Numbers; Midterm Exam
9	3/26	Intro to Data Path & Control
10, 11, 12	4/2, 4/9, 4/16	The Processor — Data Path & Control; Interrupts
13	4/23	Memory Hierarchies (Caching) Part 1
14	4/30	Memory Hierarchies (Caching) Part 2
15	5/14, 5/15	Cumulative Final Exam & Final Project Submission

Follow the link above to the respective week’s materials below.

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Week 1 — 1/22 — Verilog; Computer Abstraction & Stored Program Concept

Let’s begin

Have a read of our opening prologue, and then let’s get started with why we are taking this class…

Topics

1. Computer Abstraction
2. Stored Program Concept
3. History of computer architecture and modern advancements

Topic Deep Dive

See notes_week_01

Reading Assignment

• Read sections Chap 2.1-2.7 in the textbook handout for chapter 2, along with my summary notes handout Prof’s Notes on Comp Arch

Homework Assignment

See hw-01; solution

Week 2 — 1/29 — Instructions —The Language & Grammar of Computers — Part 1

Topics

1. Recap: Stored Program Concept, and the history of computer architecture and modern advancements
2. The alphabet, vocabulary, grammar of computers
   1. 1s and 0s as the alphabet
   2. compute and memory instructions as the vocabulary
   3. implementation of compute and memory instructions as the grammar
3. Introducing the instructions of a computer delivered by the architecture
   1. Operations of the computer hardware
   2. Operands of the computer hardware
   3. Signed and unsigned numbers
   4. Representing instructions in the computer
   5. Logical operations

Topic Deep Dive

See notes_week_02

Reading Assignment

• Read sections Chap 2.1-2.7 in my notes handout Prof’s Notes on Comp Arch, and these notes follow exactly from the MIPS textbook’s Chapter 2 and its 22 sections. I suggest reading the textbook sections too.
• Follow along with our textbook’s Chapter 2 slide deck

Homework Assignment

See hw-02; solution

Week 3 — 2/5 — Instructions —The Language & Grammar of Computers — Part 2

Topics

1. Instructions for making decisions
2. Supporting procedures (aka functions) in computer hardware
3. Begin converting our instructions to control logic for computation and memory storage.

Topic Deep Dive

See notes_week_03

Software Installation

• Install the MIPS emulator SPIM on your computer, either the SPIM GUI called “QtSPIM” or the CLI program spim. Here is the installation for the GUI program and for the CLI program

Reading Assignment

• Read Prof’s CPU Design Guide
• Read sections Chap 2.7 through Chap 2.10 in my notes handout Prof’s Notes on Comp Arch, and these notes follow exactly from the MIPS textbook’s Chapter 2 and its 22 sections. I suggest reading the textbook sections too.
• Read Chapters 3 and 4 in Introduction to MIPS Assembly Language Programming
• Continue to follow along with our textbook’s Chapter 2 slide deck

NOTE: Check our shared Teams drive for these files too as well as the installation for our software.

Homework Assignment

See hw-03; solution

Week 4 — 2/12 — Hardware Modeling with Verilog HDL — Part 1

Topics

1. Verilog: Parameterization; Built-in primitives; User-defined primitives; Dataflow modeling
2. Intro to logic design using Verilog HDL
3. Logic elements
4. Expressions
5. Modules and ports

Topic Deep Dive

See notes_week_04

Software Installation

• Verilog
  • Follow instructions here
• Build files
  
  • Unix (MacOS, Linux)
    • Makefile
  • Windows
    • makefile.ps1

Homework Assignment

See hw-04; solution

Week 5 — 2/19 — Hardware Modeling — Part 2

Topics

1. Built-in primitives
2. User-defined primitives
3. Dataflow modeling

Topic Deep Dive

See notes_week_05

Homework Assignment

See hw-05.md; solution

Week 6 — 2/26 — Intro to Assembly Language Programming — MIPS CPU; Part 1

Topics

1. Programming MIPS assembly language, using MIPS emulator (spim)

Topic Deep Dive

See notes_week_06

Reading Assignment

• Read sections Chap 2.12 through Chap 2.14 in my notes handout Prof’s Notes on Comp Arch
• Read class notes on MIPS assembly programming

Week 7 — 3/5 — Intro to Assembly Language Programming — MIPS CPU; Part 2

Topics

1. Programming MIPS assembly language, using MIPS emulator (spim)

Topic Deep Dive

See notes_week_07

Reading Assignment

• Read sections Chap 2.12 through Chap 2.14 in my notes handout Prof’s Notes on Comp Arch
• Read class notes on MIPS assembly programming

Week 8 — 3/12 — Arithmetic and Floating Point Numbers; Midterm Exam

Topics

1. Reviewing what it means for a computer to perform arithmetic
2. Addition and Subtraction
3. Multiplication
4. Division
5. A better system to handle very small and very large numbers — floating point numbers (IEEE 754 standard).
6. Arithmetic of floating point numbers.

Topic Deep Dive

See notes_week_08

Reading Assignment

• Read Chapter 3, Sections 3.1 through 3.5 in Computer Organization and Design - MIPS Edition.

Week 9 — 3/26 — Intro to Data Path & Control (Part 1 of 3)

Topics

1. Introduction to the basic MIPS processor implementation (Section 4.1).
2. Logic design conventions and clocking methodology (Section 4.2).
3. Building a simple single-cycle datapath and the Control Unit (Section 4.3).
4. Retrospective: SystemVerilog behavioral modeling of the datapath logic.

Topic Deep Dive

See notes_week_09

Reading Assignment

• Read Chapter 4, Sections 4.1 through 4.3 in Computer Organization and Design - MIPS Edition.

Week 10 — 4/2 — The Processor — Datapath & Control (Part 2 of 3)

Topics

1. The limitations of single-cycle implementation.
2. Transitioning to multicycle implementations.
3. Introduction to Pipelining.

Topic Deep Dive

See notes_week_10

Reading Assignment

• Read Chapter 4, Sections 4.4 and 4.5 in Computer Organization and Design - MIPS Edition.

Homework Assignment

See hw-10

Week 11 — 4/9 — The Processor — Datapath & Control (Part 3 of 3)

High-Level Topics: Pipelined Datapath and Control

• Pipelined Datapath and Control (Section 4.6): Transitioning to a 5-stage concurrent architecture utilizing explicit pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB).
• Data Hazards - Forwarding vs. Stalling (Section 4.7): Resolving Read-After-Write (RAW) logic overlaps via algorithmic operand forwarding pathways versus forced pipeline stalls.
• Control Hazards and Exceptions (Sections 4.8, 4.9): Coping with branch penalties, target predictions (beq), pipeline flush mechanics, and synchronous hardware exceptions.

See notes_week_11

Week 12 — 4/16 — The Processor — Exceptions and Interrupts

High-Level Topics: Exceptions, Interrupts, and Architecture Synthesis

• Handling Hardware Faults (Section 4.9): Triggering asynchronous interrupts and exceptions via Exception_Flag, performing pipeline flushes (flushD/E), and precisely capturing failing logic pointers via the EPC register.
• Comprehensive Assembly Analysis: Executing fully-simulated MIPS physical workloads mapped across linear bounds, nested logic flows, branch dependencies, and OS Vector limits.
• Pipelined Datapath Verification: Generating executable .vcd structural logs tracking signals across time bounds and inspecting exact exception fault latency tracking using the VS Code *Surfer* waveform extension.
• SystemVerilog Integration: Fortifying processor matrices globally spanning memory depth scaling mapping arrays cleanly to OS mappings (0x8000 0180), decoupling overlapping arithmetic units globally (MULT, DIV, logic arrays) preventing hardware routing collisions seamlessly natively.

See notes_week_12

Homework Assignment

See hw-12

Week 13 — 4/23 — Memory Hierarchies (Caching) Part 1

High-Level Topics: Memory Technologies and Basics of Caches

• Introduction to Memory Hierarchy (Section 5.1): The principle of locality (temporal and spatial).
• Memory Technologies (Section 5.2): SRAM, DRAM, Flash, and Magnetic Disk.
• The Basics of Caches (Section 5.3): Direct-mapped caches, tags, valid bits, block size, and cache misses.
• SystemVerilog Implementation (Section 5.4): Building Direct-Mapped, Set-Associative, and Fully Associative cache arrays in RTL.
• Hardware Simulation (Section 5.5): Proving the Iron Law of Performance via cache bypass testing and temporal locality benchmarks.

See notes_week_13

Week 14 — 4/30 — Memory Hierarchies (Caching) Part 2

High-Level Topics: Measuring and Improving Cache Performance

• Measuring and Improving Cache Performance (Section 5.4): CPU time, miss penalty, average memory access time.
• Dependable Memory Hierarchy (Section 5.5): Reliability, availability, Hamming codes.
• Virtual Memory (Section 5.6): Pages, page faults, TLB, integration of virtual memory and caches.

See notes_week_14

Week 15 — 5/14 & 5/15 — Cumulative Final Exam & Final Project Submission

• 5/14: Cumulative Final Exam.
• 5/15: Group Final Project due no later than 5pm ET.

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