<5 points>
| Total points | Explanation |
|---|---|
| 0 | Not handed in |
| 1 | Handed in late |
| 2 | Handed in on time, not every problem fully worked through and clearly identifying the solution |
| 3 | Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly |
| 4 | Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through |
| 5 | Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through. |
1. Assignment Rules and Dataflow
assign), blocking (=), and non-blocking (<=) assignments to prevent simulation race conditions.You are reviewing a peer’s SystemVerilog code for a simple positive-edge triggered D-Flip-Flop.
module flawed_dff (output logic q, input logic clk, d);
always_ff @(posedge clk) begin
q = d;
end
endmodule
(a) According to the “Golden Rules” of SystemVerilog assignments discussed in Week 5, what is dangerously wrong with this module?
(b) Rewrite the module to correctly model sequential logic.
(c) Write a single, concise assign statement (Dataflow modeling) to create a 2-to-4 Decoder’s dec[2] output. The output dec[2] should be High (1) ONLY when a 2-bit select signal sel is equal to 2'b10.
2. User-Defined Primitives (UDPs)
module logic.Built-in gate primitives (and, or) are useful, but User-Defined Primitives (UDPs) allow extreme optimization via truth tables.
(Note for first-year students: A Majority Gate is a logic circuit that acts basically like a voting system. If you have 3 inputs (A, B, and C), the gate “counts the votes” of how many inputs are High (1). If the *majority of the inputs are 1 (meaning 2 or 3 of them are High), the gate outputs a 1. If the majority are 0, it outputs a 0!)*
Write the primitive ... endprimitive block for a custom 3-input Combinational Majority Gate (maj3_udp).
a, b, cytable to implement the voting logic described above.3. MIPS 32-Bit Addressing
Because MIPS instructions are rigidly 32 bits long, an I-Type instruction cannot physically hold both the opcode and a 32-bit constant.
a) Write the exact two MIPS assembly instructions (lui and ori) necessary to load the 32-bit hexadecimal constant 0xCAFEBABE into register $t0.
b) Assume the Program Counter (PC) currently sits at memory address 0x00400040. The CPU executes a beq instruction with a 16-bit offset of 0x0008 that evaluates to true. Mathematically calculate the exact 32-bit target memory address the CPU will branch to. (Hint: Remember the PC + 4 and “shift left 2” rules for PC-Relative addressing).
4. Multicore Synchronization and Data Races
In modern multicore processors, multiple CPUs sharing mainstream Memory introduces the “Data Race” problem.
a) Explain why a standard sequence of lw (to check a lock variable) and sw (to claim the lock variable) fails to create a secure, reliable lock across multiple operating threads natively.
b) Briefly explain how the MIPS hardware instructions ll (Load Linked) and sc (Store Conditional) solve this race condition. What happens if an sc command fails?
Submit your answers as a PDF or Markdown file in the Microsoft Teams assignment tab of our course. For the coding problems (1 & 2), you may paste your SystemVerilog code directly into the document.