Courses & Projects by Rob Marano

Assignment 12: Exceptions and Interrupts

<5 points>

Homework Pointing Scheme

Total points	Explanation
0	Not handed in
1	Handed in late
2	Handed in on time, not every problem fully worked through and clearly identifying the solution
3	Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly
4	Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through
5	Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through.

Reading

Computer Organization and Design (6th Edition) Chapter 4, Section 4.9.

Formal Guidelines

State boolean logic sequences mapping datapath architectures clearly.
SystemVerilog logic explicitly modeling internal hardware mechanics must compile synchronously against generic representations.

Part 1: Distinguishing Interrupts and Exceptions (Easy)

Problem 1.1

Define the architectural contrast separating MIPS Exception sequences from MIPS Interrupts natively. List one classical instance triggering each bounds specifically.

Part 2: EPC Memory Tracking Arrays (Medium)

Assume the pipeline is decoding the following native execution sequence starting at specific address limits:

0x00400030: and $t0, $s1, $s2
0x00400034: or $t1, $s3, $s4
0x00400038: add $t2, $s5, $s6 (Triggers Arithmetic Overflow Exception inside EX stage)
0x0040003C: sub $t3, $s7, $t8

Problem 2.1

When the exception resolves inside the EX stage, what exact numerical hexadecimal structure evaluates and logs internally into the EPC mapping register bound?

Problem 2.2

Where does the overall processor natively redirect the PC to evaluate OS exception recovery code procedures locally?

Part 3: Modifying SystemVerilog Synthesized Datapaths (Hard)

Problem 3.1

Write the SystemVerilog combinational logic block connecting the PC multiplexer (NextPC) to properly route three inputs: the sequential PCPlus4F, the logical PCBranchE parameter, and the newly established OS target constant 0x8000_0180 activated sequentially via a boolean Exception_Flag vector bounds logic.

Problem 3.2

Exceptions destroy overlap trailing states. What specific boolean pin logic triggers must be mathematically forced active on the internal CPU pipeline registers to clear the subsequent corrupt instructions lingering locally?

Part 4: Conceptual Synthesis of HDL Mechanics (Conceptual)

Problem 4.1

Explain fundamentally why writing datapath matrices within a Hardware Description Language (HDL) natively mapping to von Neumann paradigms permits both testing capabilities locally AND physical processor fabrication parameters across actual silicon IC layouts directly.

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