<5 points>
| Total points | Explanation |
|---|---|
| 0 | Not handed in |
| 1 | Handed in late |
| 2 | Handed in on time, not every problem fully worked through and clearly identifying the solution |
| 3 | Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly |
| 4 | Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through |
| 5 | Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through. |
Computer Organization and Design (6th Edition) Chapter 4, Sections 4.4 and 4.5.
always_comb) and sequential (always_ff) logic blocks.Assume a custom silicon processor possesses the following absolute functional component latencies:
If this machine implements the Single-Cycle Datapath, what is the minimum safe global Clock Cycle Time ($T_c$) necessary to execute a worst-case lw instruction?
If the structural datapath is refactored into a Multicycle scheme, what is the optimal maximum clock frequency ($f_c$) of the processor?
Suppose the processor fetches a standard sw $t1, 100($t2) instruction during State 0 (Fetch).
Identify what is physically residing in the A and B internal holding registers at the end of State 1 (Decode).
In State 2 (Execution Phase), the ALU computes the destination memory target. Which MUX control values (ALUSrcA and ALUSrcB) must the Main Control Unit assert to route the correct signals into the ALU ports?
An architect wants to add an add immediate (addi) instruction to the Multicycle Control FSM. In MIPS, addi ($R[rt] = R[rs] + Imm$) behaves similarly to an R-type instruction, except it routes from the sign-extended immediate payload instead of Register B.
Write down the state transition mapping required by addi. State 0 and State 1 are universal. What occurs in State 2 and State 3 for an addi calculation, and what flag asserts write-back completion?
Provide the SystemVerilog snippets that map the addi OP-code branch (assume OP = 6'b001000) inside the next_state combinational evaluation case statement, assuming you define two new states: ADDI_EXEC and ADDI_WRITEBACK.
Suppose a pipelined processor is executing the following two instructions sequentially:
add $t0, $t1, $t2sub $t3, $t0, $t4Based on the multicycle stage progression (Fetch $\to$ Decode $\to$ Execute $\to$ Memory $\to$ Write Back), during which physical stage does the add instruction actually write its computed output into $t0?
During which physical stage does the sub instruction attempt to read the value of $t0?
Based on your answers to 4.1 and 4.2, explain the timing wait-state issue (Data Hazard) that occurs when overlapping these two instructions in a physical pipeline.