Courses & Projects by Rob Marano

Assignment 9

<5 points>

Homework Pointing Scheme

Total points	Explanation
0	Not handed in
1	Handed in late
2	Handed in on time, not every problem fully worked through and clearly identifying the solution
3	Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly
4	Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through
5	Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through.

Reading

• Notes: Week 9 Notes
• Reference: Computer Organization and Design (6th Ed.) - Chapter 4

Problem Set

Part 1: Datapath Logic & Component Utilization

1. Datapath Component Pathways (Based on textbook Ex. 4.3)

Goal: Understand structural hardware efficiency depending dynamically on the instruction workload.

Consider a baseline MIPS processor executing a computationally heavy application with the following instruction mix:

• 35% ALU (R-type operations like add, sub)
• 20% Load (lw)
• 15% Store (sw)
• 15% Branch (beq)
• 15% Jump (j)

Using this specific instruction mix, calculate the overall fractional utilization for the following major datapath elements during the application’s runtime. Show your component tracing logic based on whether each instruction type activates it.

• A. The Instruction Memory unit.
• B. The Data Memory unit.
• C. The Sign-Extend unit.

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Part 2: Single-Cycle Instruction Tracing

2. Tracing the MUXes and ALU (Based on textbook Ex. 4.5)

Goal: Trace specific, bit-level hardware controls that trigger sequentially inside the processor during a single clock cycle.

Assume it is the start of a clock cycle. The Program Counter (PC) currently holds the address 0x00400010. The processor fetches the following 32-bit machine code instruction word from Instruction Memory: 0x00c6ba22

(Hint: first decode this native hex into binary, and parse it using the MIPS 32-bit instruction formats: Opcode, rs, rt, rd, shamt, funct).

• A. What exact MIPS assembly instruction does this hex code represent?
• B. To successfully execute this instruction, what specific logical values (0 or 1) must the Main Control Unit broadcast to the three primary Multiplexers (MUXes): ALUSrc, MemtoReg, and Branch?
• C. What is the final updated value of the Program Counter (PC) safely locked in at the very end of this clock cycle (written in hex)? Name the specific Datapath Adder that mathematically computed this finalized value.

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Part 3: Timing & Critical Paths

3. Datapath Component Latencies (Based on textbook Ex. 4.7)

Goal: Calculate pure hardware latency using the critical path delays of logic gates, leading into the requirement for pipelining.

Assume you are given raw silicon components with the exact following hardware delay latencies required to physically stabilize a signal:

Component	Latency Delay
I-Mem (Instruction Fetch)	250 ps
D-Mem (Data Memory Read/Write)	250 ps
ALU (Math execution)	200 ps
PC/Adders (Address computation)	150 ps
Register File (Read or Setup Write)	150 ps
Multiplexer (MUX toggle)	25 ps
Sign-Extend Unit	20 ps
Logic Gates (e.g. AND gate)	5 ps
PC Register (clk-to-Q trigger)	30 ps
PC Register / Reg File Setup Time	20 ps

• A. Calculate the cumulative critical path execution latency (in picoseconds) logically required to safely execute a standard MIPS R-Type instruction (like add).
• B. Calculate the cumulative critical path execution latency required to logically execute a Load Word (lw) instruction.
• C. Using the timing rules of Single-Cycle Datapath Design, what MUST the processor’s universal Clock Cycle time be locked at to guarantee functional stability across the entire ISA? Explain why.

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Submission

Submit your answers as a PDF or Markdown file via the Microsoft Teams’ assignment. Be sure to clearly box your final mathematical outputs where applicable.

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