Courses & Projects by Rob Marano

Assignment 7

<5 points>

Homework Pointing Scheme

Total points	Explanation
0	Not handed in
1	Handed in late
2	Handed in on time, not every problem fully worked through and clearly identifying the solution
3	Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly
4	Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through
5	Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through.

Reading

• Notes: Week 7 Notes
• Reference: MIPS Green Sheet

Problem Set

Part 1: Advanced Assembly & Hardware Profiling

1. The Cost of Hardware Execution

Goal: Understand why instruction count in a software emulator like SPIM does not natively equate to physical hardware latency on silicon.

In our analysis of the Quake III Arena Fast Inverse Square Root algorithm, we replaced a standard 2-instruction IEEE-754 sequence (sqrt.s followed by div.s) with a 14-instruction sequence utilizing integer and bitwise manipulation (srl, sub, mul.s).

• A. If you run both algorithms sequentially 100,000 times in the SPIM software emulator, the 2-instruction standard approach finishes almost 3x faster. Remember that Emulator Timing Abstraction signifies the mathematical reality that software emulators natively execute all assembly instructions as 1 equal software “step” regardless of physical hardware complexity. Explain why this abstraction misrepresents true hardware performance in this example.
• B. Explain the engineering and hardware justification behind Quake developers choosing to execute 14 separate instructions instead of relying on the single, highly accurate div.s instruction on 1999 silicon (like the MIPS R4000).

2. Exception Handling Architecture

Goal: Identify how the MIPS ISA mechanically handles fatal hardware faults or OS-level interrupts during runtime execution.

When an unaligned memory access (Address Error) or an arithmetic anomaly (Overflow) occurs, standard user-space execution is halted.

• Describe the architectural role of Coprocessor 0 (CP0) and the .ktext memory segment in capturing and resolving the fault.
• What explicitly happens to the user program’s PC (Program Counter) when SPIM’s exceptions.s kernel handler takes over?

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Part 2: Final Project & Midterm Readiness

3. ISA Design and Bit Constraints

Goal: Evaluate the architectural layout of custom instruction widths for your impending Final Project ISA.

For your Final Project, you are structurally required to design an Instruction Set Architecture (ISA). Assume you are building a strict 32-bit width instruction format similar to MIPS.

You decide you want your CPU to support immediately loading massively large constant numbers directly inside an I-Type instruction. To do this, you assign 24 bits out of the 32 purely to the “Immediate” field.

• Mathematically, how does this 24-bit immediate field explicitly constrain the remaining bits available for your Opcode and Register addresses?
• What is the architectural consequence of this decision on the total number of unique registers your CPU can physically wire up?

4. MIPS Dataflow & Recursion

Goal: Solidify execution chains, Stack Pointer ($sp) usage, and Return Address ($ra) logic for the midterm.

A student writes a MIPS procedure that recursively calls itself to calculate the Fibonacci sequence. However, before executing the jal instruction to jump back into its own loop, the student completely forgets to use the $sp (Stack Pointer).

Here is the student’s broken fib procedure:

fib:
    # Base cases: if n == 0 return 0, if n == 1 return 1
    beq  $a0, 0, fib_zero
    beq  $a0, 1, fib_one
    
    # Missing: addi $sp, $sp, -12
    # Missing: sw $ra, 8($sp), sw $s0, 4($sp), sw $a0, 0($sp)
    
    addi $a0, $a0, -1      # n - 1
    jal  fib               # First recursive call
    
    move $s0, $v0          # Store result of fib(n-1) in $s0
    
    addi $a0, $a0, -1      # n - 2 (since $a0 is already n-1)
    jal  fib               # Second recursive call
    
    add  $v0, $s0, $v0     # fib(n-1) + fib(n-2)
    
    # Missing: lw $ra, 8($sp), lw $s0, 4($sp), lw $a0, 0($sp)
    # Missing: addi $sp, $sp, 12
    
    jr   $ra

fib_zero:
    li   $v0, 0
    jr   $ra

fib_one:
    li   $v0, 1
    jr   $ra

• What specific mechanical hardware state is catastrophically overwritten when the second jal executes?
• Explain precisely how this omission destroys the jr $ra execution chain when the recursion finally hits its base case and attempts to unfold back to the main procedure.

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Submission

Submit your answers as a PDF or Markdown file via the GitHub Classroom repository link provided directly in Microsoft Teams. Be sure to clearly box your final mathematical outputs where applicable.

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