<5 points>
| Total points | Explanation |
|---|---|
| 0 | Not handed in |
| 1 | Handed in late |
| 2 | Handed in on time, not every problem fully worked through and clearly identifying the solution |
| 3 | Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly |
| 4 | Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through |
| 5 | Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through. |
1. Assessing CPU Performance
Goal: Solidify the mathematical performance bottlenecks associated with executing every instruction in exactly one fixed-length hardware clock cycle.
You are evaluating the performance of a strict Single-Cycle Processor running a MIPS Assembly program block. The hardware engineers have fixed the Clock Cycle Time to exactly 800ps (picoseconds).
Consider the following program:
lw $t0, 0($a0)
add $t0, $t0, $t1
sw $t0, 0($a0)
Using the Classic CPU Performance Equation (Execution Time = Instruction Count x CPI x Clock Cycle Time), calculate the total execution time of this block. Briefly explain why the CPI value must natively be what it is on this specific processor design.
2. The MIPS Memory Layout
Goal: Differentiate how structural hardware addresses cleanly separate static data, dynamic space, execution logic, and functional hierarchy.
The Operating System formally assigns your MIPS program distinct segmented spaces in Main Memory. Match the following four localized behaviors to the specific structural segment they reside in (Text, Data, Heap, or Stack):
add instruction that your CPU fetches to execute.malloc().msg: .asciiz "Hello, World!\n" declared rigidly in your source code.$ra) history generated when you manually subtract from the $sp pointer during a deep nested procedure.3. Procedure Calls and the Stack
Goal: Identify the exact mechanical hardware loss that occurs when nested functions fail to manually spill their state to the stack.
A developer wrote a nested procedure (a function that calls another function). They executed a jal command to enter their first function, immediately did some math on $a0, and then executed a second jal command to enter a helper function.
When the helper function finished and initiated its jr $ra return, the program entirely crashed, losing track of where it was supposed to return to in main.
What explicitly happened to the $ra register when the second jal executed, and what standard Stack Pointer ($sp) commands was the developer required to use beforehand to prevent this catastrophic memory loss?
4. Branching and The Pipelining Teaser
Goal: Transition understanding from linear code execution to the exact mathematical offsets the CPU calculates when dynamically leaping across memory address space.
To calculate target destinations, branches and jumps utilize mechanically distinct paradigms. PC-Relative Addressing calculates a branch offset locally relative to the current Program Counter (PC + 4 + offset). Pseudodirect Addressing calculates a jump by explicitly replacing the lower 28 bits of the Program Counter with an absolute target block.
To prepare for our Chapter 4 introduction to Pipelining, we must explicitly understand where the Program Counter (PC register) points.
beq branch instruction (in the “branch delay slot”), what is the relative value of the PC evaluated natively by the hardware before shifting?Submit your answers as a PDF or Markdown file. Be sure to clearly box your final mathematical output for Problem 1.