<5 points> see pointing scheme
These remain same as last week since we are expanding on SystemVerilog work.
Reading links are stored on our course’s Teams instance.
GitHub Classroom Assignment Link: https://classroom.github.com/a/XC_j3CKm
You will do all your work, store it in the GitHub Classroom repo that you get when following the assignment link.
From now on, you will write your homework answers using Markdown in the README.md file in your individual GitHub repository you get from the GitHub Classroom assignment. See [homework 1 solution file](/courses/ece251/2025/assignments/hw-01-solution.html) as an example format. You will then submit your assignment using GitHub Classroom repo by adding your repo files, committing those files, then pushing your repo to GitHub — you'll do this with the git` command. Come see me if you still do not understand how to do this.
Using Behavioral Modeling in SystemVerilog, create the following modules that will be used in your final project — your CPU and memory design of your own computer. Parameterize your bit length so that you can define any bit size in your test bench, not hardcoding that in your module definition. Use 8-bits are the default bit length.
clock, reset, enable, incrementclock, reset, enableclock, reset, enable| Total points | Explanation |
|---|---|
| 0 | Not handed in |
| 1 | Handed in late |
| 2 | Handed in on time, not every problem fully worked through and clearly identifying the solution |
| 3 | Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly |
| 4 | Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through |
| 5 | Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through. |