Musings, Courses, & Projects by Rob Marano

Assignment 1

<5 points>

Homework Pointing Scheme

Total points Explanation
0 Not handed in
1 Handed in late
2 Handed in on time, not every problem fully worked through and clearly identifying the solution
3 Handed in on time, each problem answered a boxed answer, each problems answered with a clearly worked through solution, and less than majority of problems answered correctly
4 Handed in on time, majority of problems answered correctly, each solution boxed clearly, and each problem fully worked through
5 Handed in on time, every problem answered correctly, every solution boxed clearly, and every problem fully worked through.

Reading

Reading links are stored on our course’s Teams instance.

  1. Basic Structure of Computers
  2. Hardware Description Language primer
  3. Review of Digital Logic Circuits
  4. <optional, supporting> Comprehensive Verilog Training Manual (from 2001)

Software Installation

Homework Assignment

GitHub Classroom Assignment Link: https://classroom.github.com/a/GSFzh7kV

Write up your solution on paper then scan into a PDF or write in an editor then export to a PDF. Then add the PDF to the GitHub Classroom assignment repository. Remember to just add the GitHub repository to the Microsoft Team’s assignment from here.

Problem Set

  1. Convert the following pairs of decimal number to 6-bit 2’s-complement numbers. Then perform addition and subtraction on each pair. Indicate whether or not overlow occurs for each case.
    1. 16 and 29
    2. -26 and 19
  2. Create the module and test bench in SystemVerilog for the following digital circuits; you must use the Verilog module template and the Verilog test bench template. Each module will have its own directory. Therefore, for each module, you will also need include the command-line build files, as we discussed in class.
    For Windows, config.ps1 where you define your module name; clean.ps1; display.ps1; and makefile.ps1. For Linux and MacOS, make sure you install make, and you’ll need this for each module Makefile, one in each module directory; don’t forget to rename your module in the Makefile.
    1. 4-to-1 multiplexer, using gate-level modeling
    2. 4-bit decoder, using behavioral modeling
    3. 4-bit full adder, using gate-level modeling
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