Musings, Courses, & Projects by Rob Marano

Assignment 2

<45 points>

Instructions

For this assignment, you will start building out your SystemVerilog catalog of digital circuit components that you will use in your final project designing a computer (CPU+memory+data path+input/output).

You will create your catalog and its components in a GitHub repository. Please follow this link to create your own repo in our course’s account:

https://classroom.github.com/a/WcKVdfxS

You will each create the following catalog components for this assignment in your repository. Each component will be parameterized with default 8-bit side operands (number bit width), include enable and reset, and ensure your test bench just tests for the ranges of values constrained to the bit width (hint, use for loop):

  1. clock
  2. (up/down) counter
  3. D flip flop
  4. full adder
  5. shift logic left by n bits
  6. shift logic right by n bits
  7. sign extension
  8. 2:1 multiplexer
  9. 4:1 multiplexer

After you signup for the GitHub Classroom repo, you will have your own repo.

Clone your repo using git to your computer.

Create the following directory structure in your repo:

./your_repo
./your_repo/catalog
./your_repo/catalog/clock
./your_repo/catalog/counter
./your_repo/catalog/dff
./your_repo/catalog/adder
./your_repo/catalog/sll
./your_repo/catalog/slr
./your_repo/catalog/signext
./your_repo/catalog/mux_2to1
./your_repo/catalog/mux_4to1

These will have been created in your template.

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